1. Field of the Invention
The present invention relates to microcontrollers. More specifically, the present invention relates to a dual bus matrix architecture for microcontrollers.
2. Background
The increasing number of peripherals connected onto a system bus creates routability problems. Moreover, the data path size of peripherals may not be the same due to their different inherent bandwidth requirements. When interconnecting all of these heterogeneous peripherals to the same bus matrix, it may be difficult to match all the requirements. These requirements may include, but are not limited to, maximum frequency and routability. Although, wrapper logic may be added, it can lead to a reduction in performance.
Currently, high-end microcontrollers use a single bus matrix because it is sufficient to cover the needs of today's applications. However, increasing demands for portable multimedia applications require more peripherals of heterogeneous bandwidth requirements and different clock frequencies to achieve appropriate bandwidth with optimal power consumption.